1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor memory device with strengthened power and a method of strengthening the power of a semiconductor memory device.
2. Description of the Related Art
Semiconductor memory devices are commonly arranged according to several data bit configurations, referred to as “organizations”. For instance, semiconductor memory devices can be arranged according to X4, X8, and X16 data bit organizations. In the X4 data bit organization, the data bandwidth, i.e., the number of bits of data, which is to be simultaneously input to and output from the semiconductor memory device, is 4 bits. In the X8 data bit organization, the data bandwidth is 8 bits, and in the X16 data bit organization, the data bandwidth is 16 bits.
Accordingly, the number of data input/output (I/O) pads, and the bonding arrangements among the data I/O pads and pins of a semiconductor memory package vary according to the type of organization. Semiconductor memory devices can include various organizations within a chip, but the package is designed according to an organization in which data bandwidth can be maximized.
FIG. 1 is a view of a bonding configuration for an X4 organization of a conventional semiconductor memory device. Referring to FIG. 1, data I/O pads PAD_LDQ0 through PAD_LDQ3 used in the X4 organization are bonded to corresponding data I/O pins LDQ0 through LDQ3 of a package. The other data I/O pads PAD_LDQ4 through PAD_LDQ7 and PAD_UDQ0 through PAD_UDQ7, which are not used in the X4 organization but are used in the X8 and X16 organizations, are not connected to their corresponding data I/O pins. That is, the data I/O pads PAD_LDQ4 through PAD_LDQ7 and PAD_UDQ0 through PAD_UDQ7 are in a no connection (NC) state.
FIG. 2 is a view of a bonding configuration for the X8 organization of a conventional semiconductor memory device. Referring to FIG. 2, in the X8 organization, data I/O pads PAD_LDQ0 through PAD_LDQ7 are bonded to corresponding data I/O pins LDQ0 through LDQ7 of a package. The other data I/O pads PAD_UDQ0 through PAD_UDQ7 are not connected to data I/O pins, that is, they are in the NC state.
FIG. 3 is a block diagram of a data I/O driver 300 connected to data I/O pads of a conventional semiconductor memory device, which are in the NC state. The data I/O driver 300 includes an output buffer 31 whose output terminal is connected to a corresponding pad PAD_UDQ; an input buffer 32 whose input terminal is connected to the pad PAD_UDQ; and an NMOS transistor 33 for the purpose of electrostatic discharge (ESD) protection, which is connected between the pad PAD_UDQ and a ground voltage line VSS.
However, since some of data I/O pads of a conventional semiconductor memory device are in the NC state, the use efficiency of the data I/O pads is low. In general, the greater the bandwidth of a memory device, i.e., the bit value of data to be simultaneously input to and output from the semiconductor memory device, the more that power noise, such as ground bounce, can have an effect on system operation. Also, in general, the lower a power supply voltage, the greater the level of power noise.